1. Field of the Invention
The present invention relates to a memory device, and more particularly to a synchronous memory device with a dual sensing output path having two data paths, each of which has a latch circuit and a sense amplifier.
2. Description of Related Arts
In general, an output circuit on a read path of a synchronous memory controls the transmission of data read out from a memory cell. Accordingly, its performance depends on the increase of data transmission rate and a loss of data.
FIG. 1 is a schematic block diagram illustrating a read operation in a conventional synchronous memory device. As shown in FIG. 1, the conventional synchronous memory device has widely used an output register 20 controlled by an external clock K. The word line WL is activated and the a memory cell in a memory cell array 10 is selected. The data stored in the selected memory cell is transferred to a sense amplifier 14 through an Y-transfer gate 12. The data amplified by the sense amplifier 14 is stored in the latch circuit 16 which includes two inverters 17 and 19 and the latched data is input into the output register 20 controlled by the external clock K. When the clock K is in a high level, the data is transferred from the output register 20 to an output buffer 40.
Referring now to FIG. 2, if the word line is activated in response to the external clock K and address signals, the data stored in a selected memory cell is output to node N1 and the output data is amplified by the sense amplifier 14 and then the output from the sense amplifier 14 is transferred to node N2. The data at node N2 is transferred to the output buffer 40 via the output register 20.
However, if the output register operates before the output from the memory cell is transferred to the latch circuit through the sense amplifier, the output buffer can receive an erroneous data. Therefore, the external clock K is restricted in speed because the external clock K should not be applied the output register until the output from the sense amplifier is stored in the latch circuit. This restriction cause an problem not to make a cycle time of the memory device fast.